Tuesday, June 30, 2009
Finished the complete SoC (system on chip) design for this 'ere project, which I think is quite impressive in only a couple of weeks given how complicated it all turned out to be.
I can see me using verilog in preference to VHDL in future, I've found it fairly nice to use. There was always something a little counter-intuitive about VHDL as far as I was concerned...
And now onward and downward - the application software for it.