Saturday, June 27, 2009

Standards? What are they, exactly?

I've got to design an SPI port; they have a clock line, a data in and a data out line. Oh, and a chip select line. Four lines, in all. Should be easy enough to knock one up.

Of course it's too much to expect that I'll have been given any documentation for the device that it needs to interface with so I'd better make the port flexible. How many variations can there be?

Turns out there are chips out there with every possible variation of those signals. The chip select can be active high or active low. The clock line can be active high or active low and the input data can be latched on the rising edge, or the falling edge... The output data can change before the leading or after the trailing edge of the clock. The clock may or may not run when the chip select isn't active. The number of bits in each transaction? You think it's a constant? Foolish twisted boy...

Standards? Simplicity? Who needs 'em...

[weeks later]

I didn't make it clear that the SPI port I was grumping about there was a slave port, designing the master end is easier (I'd designed a master port as well, both of the designs are published in the R3220 data so decide for youself)... The slave port's timing is at the mercy of the master port and I didn't have any documentation for their master port... Still, it all worked so I must have made a reasonable job of things...

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